1. Field of the Invention
This invention generally relates to a programmable semiconductor logic device which can be programmed to define a desired logic function, and, in particular, to a field programmable logic device including an AND gate array and an OR gate array, at least one of which may be programmed by a user to define a desired logic function.
2. Description of the Prior Art
A field programmable semiconductor logic device is well known in the art. And, such a programmable logic device typically includes an AND gate array (or sometimes called an AND plane) and an OR gate array (or sometimes called an OR plane). In one type of the programmable logic device, only the AND gate array is programmable and the OR gate array is fixed and thus non-programmable. In another type, both of the AND and OR gate arrays are programmable. It is to be noted that the term programmable logic array or PLD for short is used herein to embrace any type of semiconductor programmable logic devices including both AND and OR gate arrays, at least one of which is programmable by the user.
In a typical prior art field programmable logic device, input lines from an input buffer extend across product term lines of an AND-OR block, including an AND gate array and an OR gate array, and a programmable element is provided at each intersection between the product term lines and the input lines. However, a programmable logic device requiring an increased number of input/output pins has an increased number of input lines and also an increased number of product term lines. However, there is a limit for the number of input/output pins because of the availability of chip area and also the number of gates to be provided in one chip. In addition, as the number of product term lines increases, the operational speed becomes reduced. There is also a further problem of increased waste of elements because an increased proportion of the AND-OR block may be left unused depending on a desired logic function.